In many integrated circuit (IC) applications, and in particular in safety critical applications, self-testing is an essential component of an IC device, whereby one or more self-tests are executed within at least a part of the IC device. During self-test execution, the application functionality of the part of the device executing the self-test(s) is unavailable for normal (application) operation. However, for safety critical applications the availability of the application functionality is critical. Thus, a key limiting factor for self-test execution is execution time so that the amount of time the application functionality is unavailable during self-test execution is minimized.
Another limiting factor for self-test execution is power consumption, whereby the power consumption of (at least the part of) the device executing the self-test(s) must remain within a predefined power budget during self-test execution. In order to remain within a predefined power budget during self-test execution, the (or each) clock signal for the part of the device under test may need to be configured to comprise a slower clock speed to reduce the power consumption thereof. However, reducing the speed of the clock signal(s) in this manner during self-test execution will increase the self-test execution time, and thus the amount of time the application functionality is unavailable.
Conventionally, structural self-testing is executed at a fixed clock frequency. Such a fixed frequency clocking scheme provides a safe way to remain within a predefined power budget at worst-case conditions. However, a too conservative scheme can result is an unnecessarily long self-test execution time and therefore reduced availability.